1. Field of the Invention
The present invention relates generally to semiconductor devices, and more specifically, to a static random access memory (hereinafter referred to as SRAM).
2. Description of the Background Art
FIG. 20 is an equivalent circuit diagram showing an SRAM cell. The SRAM includes six transistors altogether, access transistors 1, 2 and driver transistors 3, 4 formed on a substrate, and load transistors 5, 6 formed of thin film transistors. Access transistor 1 includes a word line 7, and access transistor 2 includes a word line 8. Access transistor 1 is connected to a bit line 9, and access transistor 2 is connected to a bit line 10. In the figure, the portions designated with reference numerals 11, 12 indicate parasitic resistance in a ground line (hereinafter referred to as GND) 43.
The SRAM cell operates as follows.
In reading, voltage is applied to word lines 7, 8 to open the gate. At the time, voltages corresponding to their respective inverter states appear at bit line 9 and bit line 10. In writing, also voltage is applied to word lines 7, 8 to open the gate, and voltage corresponding to a desired state of writing is applied to bit line 9 and bit line 10.
The layout of the equivalent circuit is disclosed in IEDM 91, pp.477-484. FIGS. 21 to 23 show a layout for one conventional SRAM cell. FIG. 22 is drawn on the layout shown in FIG. 21, and the layout shown in FIG. 21 is drawn on the layout shown in FIG. 22. The SRAM includes field oxide films 13, 14, 15, active regions 16, 17, first gates 18, 19, 20, 21 formed of polysilicon or polycide, first direct contacts 22, 23 linking the active regions and the first gates, second gates 24, 25, 26 formed of polysilicon or polycide, and second direct contacts 27, 28, 29, 30 linking the active regions and the second gates.
Referring to FIG. 22, the SRAM includes third gates 31, 32 (to be the gates of TFTs) formed of polysilicon, third direct contacts 33, 34 linking the first gates and the third gates, forth gates 35, 36 (to be the channel/source/drain regions of TFTs) formed of polysilicon, and forth direct contacts 37, 38 linking the third gates and the forth gates.
Referring to FIG. 23, the SRAM includes first metal interconnection layers 39, 40 (bit lines), and contacts 41, 42 linking the second gates and the first interconnection layers.
FIG. 24 is a cross sectional view showing the SRAM in FIGS. 21 to 23 taken along line A--A.
Referring to FIGS. 20 and 24, access transistor 1 is formed of active region 16 and first gate 18. Access transistor 2 is formed of active region 17 and first gate 19. Driver transistor 3 is formed of active region 17 and first gate 20. A thin film transistor, load transistor 5 is formed of third gate 32, and forth gate (channel/source/drain region) 36. A thin film transistor, load transistor 6 is formed of third gate 31, forth gate (channel/source/drain region) 35. Word line 7 corresponds to first gate 18, and word line 8 corresponds to first gate 19. Bit line 9 corresponds to first metal interconnection layer 39, and bit line 10 corresponds to first interconnection layer 40. The GND lines 43 of the memory cell corresponds to second gate 24. The parasitic resistance 11 of GND corresponds to the resistance of second direct contact 27. The parasitic resistance 12 of GND corresponds to the resistance of second direct contact 28.
Thus structured conventional SRAM is encountered with the following problem.
Referring to FIG. 20, when a reading operation is performed with storage nodes a and b being at Low and High states, respectably column current i is passed from the bit line to GND line 43 through storage node a. At the time, if parasitic resistance 11 is large the Low level of storage node a increases, resulting in destruction of data. Accordingly, in order to keep parasitic resistance 11 small, referring to FIG. 21, second direct contacts 27, 28 are formed in a rectangular form and its area on a plane is set large. In contrast, the second direct contacts 29 and 30 of the bit line portion has a small area on a plane, because the parasitic resistance does not affect the operation.
It was however difficult to form holes of different sizes by photolithography, because with difference in quantities of light, such holes cannot be opened precisely into designed values.
FIG. 25 is a diagram showing two memory cell arrays, designating one memory cell (exclusive of parasitic resistance 11, 12 at GND) as X. A memory cell portion X.sub.a and a memory cell portion X.sub.b are provided adjacent to each other.
Referring to FIG. 25, the parasitic resistance 11, 12 of GND (in other words second direct contacts 27, 28) are shared between cell Xa and adjacent cell Xb. Therefore, in the worst case, column current i for the two cells is passed across parasitic resistance 11, 12, thus increasing the potential on the Low side of storage node and data is likely to be destroyed. Accordingly, second direct contacts 27, 28 must be formed large enough.
Note that "direct contact" herein refers to the one as shown in FIG. 26. Referring to FIG. 26, a connecting portion 102 is connected to portion 100 through a contact hole 101a provided in an interlayer insulating film 101.
For stable memory operation, as described in IEDM 91, pp.481-484 the cell ratio (=driver transistor current/access transistor current) must be large enough. Accordingly, the gate length of a driver transistor is desirably shorter, with its gate width being larger, while the gate length of an access transistor is desired to be long with its gate width being narrow. It is, however, difficult to form two kinds of gates having different gate lengths and gate widths in a memory cell, because they cannot be precisely fabricated into values as designed due to difference in quantities of exposure light in photolithography.
In addition, if the gate width of an access transistor is narrowed, the narrow channel effect occurs, which causing fluctuations of its V.sub.th only in the access transistor.
The size of a direct contact is determined based on the limit of exposure in photolithography (a minimum interval between two patterns), and the minimum width of each interconnection (each gate) is usually substantially equal to the length of a shorter side of a direct contact. Accordingly, when each interconnection is linked with a direct contact, the width of the interconnection is thickened at connecting positions taking into account registration margins for masks. Accordingly, excess spaces must be secured at such connecting positions.
Additionally, in a conventional memory cell, referring to FIG. 24, first direct contact 22, third direct contact 33 and forth direct contact 37 are formed upon each other in the vertical direction, and direct contact portion 37 is in a dented form. Therefore, the hole must be formed deep which makes etching difficult and the presence of steps reduces margins for photolithography.